Integrated circuit semiconductor device

ABSTRACT

An integrated circuit semiconductor device includes a lower electrode formed on a substrate extending in a first direction and a second direction perpendicular to the first direction and a support structure supporting the lower electrode. The support structure includes a support pattern surrounding the lower electrode, extending in the first direction and the second direction, and having a hole through which the lower electrode passes, and a concavo-convex structure having at a surface of the support pattern a plurality of convex portions extending in a third direction perpendicular to the first direction and the second direction, and a plurality of concave portions arranged between the convex portions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. § 119to Korean Patent Application No. 10-2021-0140490, filed on Oct. 20,2021, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated by reference herein in its entirety.

BACKGROUND

The inventive concept relates to an integrated circuit semiconductordevice, and more particularly, to an integrated circuit semiconductordevice including a capacitor.

With the development of electronic technologies, down-scaling ofintegrated circuit semiconductor devices has been expanded drastically,and accordingly, patterns constituting an integrated circuitsemiconductor device have also been miniaturized. In tandem with such atendency, there has been a demand for development of a structure havinga miniaturized capacitor with improved capacitance while maintainingdesired electrical properties.

SUMMARY

The inventive concept provides an integrated circuit semiconductordevice capable of preventing tilting or falling down of lower electrodeseven when a height of the lower electrodes constituting a capacitor isincreased, and is thereby capable of controlling occurrence of a bridgedefect between adjacent lower electrodes. A bridge defect refers to aphenomenon in which a leakage current is generated due to a formation ofa undesired current path (i.e., a “bridge”) between adjacent electrodes.For example, when an electrode is tilted or falls down so as to contactor become in close proximity to an adjacent electrode, an undesiredcurrent path (i.e., bridge) between the electrodes may be formed.

According to an aspect of the inventive concept, there is provided anintegrated circuit semiconductor device including a lower electrodeformed on a substrate extending in a first direction and a seconddirection perpendicular to the first direction and a support structuresupporting the lower electrode. The support structure includes a supportpattern surrounding the lower electrode, extending in the firstdirection and the second direction, and having a first hole throughwhich the lower electrode passes, and a concavo-convex structure havingat a surface of the support pattern a plurality of convex portionsextending in a third direction perpendicular to the first direction andthe second direction, and a plurality of concave portions arrangedbetween the convex portions.

According to another aspect of the inventive concept, there is providedan integrated circuit semiconductor device including: a plurality oflower electrodes spaced apart from each other on a substrate extendingin a first direction and a second direction perpendicular to the firstdirection; a support pattern extending in the first direction and thesecond direction and having a plurality of first holes through which theplurality of lower electrodes pass; and a concavo-convex structurehaving at a surface of the support pattern a plurality of convexportions extending in a third direction perpendicular to the firstdirection and the second direction, and a plurality of concave portionsarranged between the convex portions.

According to another aspect of the inventive concept, there is providedan integrated circuit semiconductor device including: a plurality oflower electrodes spaced apart from each other on a substrate extendingin a first direction and a second direction perpendicular to the firstdirection; an upper support structure including an upper support patternextending in the first direction and the second direction and having aplurality of first holes through which the plurality of lower electrodespass, and an upper concavo-convex structure having at a surface of theupper support pattern a plurality of upper convex portions extending ina third direction perpendicular to the first direction and the seconddirection, and a plurality of upper concave portions arranged betweenthe plurality of convex portions; a lower support structure including alower support pattern extending in the first direction and the seconddirection between the substrate and the upper support structure, and alower concavo-convex structure having at a surface of the lower supportpattern a plurality of lower convex portions extending in the thirddirection, and a plurality of lower concave portions arranged betweenthe lower convex portions; a dielectric film in contact with theplurality of lower electrodes, the upper support structure, and thelower support structure; and an upper electrode facing the plurality oflower electrodes with the dielectric film interposed therebetween.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive concept will be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings in which:

FIG. 1 is a schematic plan layout for explaining some components of amemory cell array area of an integrated circuit semiconductor deviceaccording to an embodiment;

FIG. 2 is a plan view showing some components of an integrated circuitsemiconductor device according to an embodiment;

FIG. 3 is a cross-sectional view schematically showing some componentsof a cross-section taken along the 1X-1X′ line of FIG. 2 ;

FIGS. 4 and 5 are enlarged cross-sectional views for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment;

FIGS. 6 and 7 are enlarged cross-sectional views for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment;

FIG. 8 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment;

FIG. 9 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment;

FIG. 10 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment;

FIG. 11 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment;

FIG. 12 is a plan view showing some components of an integrated circuitsemiconductor device according to an embodiment;

FIG. 13 is a cross-sectional view schematically showing some componentsof a cross-section taken along the 2X-2X′ line of FIG. 12 ;

FIGS. 14A to 14F are cross-sectional views illustrating a method ofmanufacturing an integrated circuit semiconductor device, according toan embodiment;

FIGS. 15A and 15B are cross-sectional views illustrating a method ofmanufacturing an integrated circuit semiconductor device, according toan embodiment;

FIG. 16 is a plan view of a memory module including an integratedcircuit semiconductor device according to the technical aspects of theinventive concept;

FIG. 17 is a schematic diagram of a memory card including an integratedcircuit semiconductor device according to the technical aspects of theinventive concept; and

FIG. 18 is a schematic diagram of a system including an integratedcircuit semiconductor device according to the technical aspects of theinventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept are described indetail with reference to the accompanying drawings. Like referencenumerals in the drawings denote like elements, and thus theirdescription will be omitted.

FIG. 1 is a schematic plan layout for explaining some components of amemory cell array area of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, an integrated circuit semiconductor device 10, forexample, a dynamic random access memory (DRAM) device, may include aplurality of active areas AC arranged to extend horizontally in adiagonal direction of an X direction and a Y direction on a plane. Aplurality of word lines WL may extend in parallel with each other in theX direction across the plurality of active areas AC. On the plurality ofword lines WL, a plurality of bit lines BL may extend in parallel witheach other in the Y direction intersecting with the X direction. Each ofthe plurality of bit lines BL may be connected to the active area ACthrough a direct contact DC.

A plurality of buried contacts BC may be formed between two adjacent bitlines among the plurality of bit lines BL. A plurality of conductivelanding pads LP may be respectively formed on the plurality of buriedcontacts BC. Each of the plurality of conductive landing pads LP may bearranged to overlap at least a portion of the buried contact BC. Aplurality of lower electrodes LE spaced apart from each other may berespectively formed on the plurality of conductive landing pads LP. Theplurality of lower electrodes LE may be connected to the plurality ofactive areas AC through the plurality of buried contacts BC and theplurality of conductive landing pads LP.

FIG. 2 is a plan view showing some components of an integrated circuitsemiconductor device according to an embodiment, and FIG. 3 is across-sectional view schematically showing some components of across-section taken along the 1X-1X′ line of FIG. 2 .

Specifically, FIG. 2 may be a plan view of an upper support structureUSS and a lower support structure LSS of FIG. 3 . An integrated circuitsemiconductor device 100 of FIGS. 2 and 3 may constitute a part of theintegrated circuit semiconductor device 10 of FIG. 1 .

Some of the components of the integrated circuit semiconductor device100 are omitted or simplified in FIGS. 2 and 3 . However, the componentsof the integrated circuit semiconductor device 100 are not limited tothe components illustrated in FIGS. 2 and 3 , and should be construed asincluding characteristic components described below.

The integrated circuit semiconductor device 100 may include a substrate110 including a plurality of active areas AC and a lower structure 120formed on the substrate 110. A plurality of conductive areas 124 maypass through the lower structure 120 and be connected to the pluralityof active areas AC.

The substrate 110 may include elemental semiconductors, such as Si andGe, or compound semiconductors, such as SiC, GaAs, InAs, and InP. Thesubstrate 110 may include a semiconductor substrate, at least oneinsulating film formed on the semiconductor substrate, or structuresincluding at least one conductive area. The conductive area may includea well doped with impurities or a structure doped with impurities. Adevice separation area 112 may be formed in the substrate 110 and definethe plurality of active areas AC. The device separation area 112 mayinclude an oxide film, a nitride film, or a combination thereof.

In some embodiments, the lower structure 120 may include a silicon oxidefilm, a silicon nitride film, or an insulating film including acombination thereof. In other embodiments, the lower structure 120 mayinclude various conductive areas, for example, a wiring layer, a contactplug, a transistor, etc., and an insulating film to insulate the variousconductive areas.

The plurality of conductive areas 124 may include polysilicon, metal,conductive metallic nitride, metal silicide, or a combination thereof.The lower structure 120 may include the plurality of bit lines BLdescribed with reference to FIG. 1 . Each of the plurality of conductiveareas 124 may include the buried contact BC and the conductive landingpad LP described with reference to FIG. 1 .

An insulating pattern 126P having a plurality of openings 126H may bearranged on the lower structure 120 and the plurality of conductiveareas 124. The insulating pattern 126P may include or may be formed of asilicon nitride film, a silicon carbon nitride film, a silicon nitridefilm including boron, or a combination thereof. Although a plurality ofthe same structures, devices, films, layers, openings, etc. are includedin the integrated semiconductor device 10, for the sake of clarity, thesingular forms “a”, “an” and “the” will be used throughout thedescription and are intended to include the plural forms as well, unlessthe context clearly indicates otherwise.

A capacitor CP1 including the lower electrode LE, a dielectric film 160,and an upper electrode UE may be arranged on the conductive area 124.Lower electrode LE may have a pillar shape extending in a direction awayfrom the substrate 110 in a vertical direction (Z direction) through theopening 126H of the insulating pattern 126P from an upper surface of theconductive area 124. The dielectric film 160 and the upper electrode UEmay be formed in this stated order on the plurality of lower electrodesLE. For example, a portion of the dielectric film 160 may be formedbetween the upper electrode UE and the lower electrode.

FIGS. 2 and 3 illustrate an example in which the lower electrode LE hasa pillar shape; however, the technical aspects of the inventive conceptare not limited thereto. For example, the lower electrode LE may have across-section structure having a cup shape or a cylindrical shape with ablocked bottom. The lower electrode LE and the upper electrode UE may bearranged to face each other with respect to the dielectric film 160.

The lower electrode LE and the upper electrode UE may respectivelyinclude or may be formed of a metal film, a conductive metal oxide film,a conductive metal nitride film, a conductive metal oxynitride film, ora combination thereof. In some embodiments, the lower electrode LE andthe upper electrode UE may each include or may be formed of Ti, Tioxide, Ti nitride, Ti oxynitride, Co, Co oxide, Co nitride, Cooxynitride, Nb, Nb oxide, Nb nitride, Nb oxynitride, Sn, Sn oxide, Snnitride, Sn oxynitride, or a combination thereof.

For example, the lower electrode LE and the upper electrode UE mayrespectively include or may be formed of TiN, CoN, NbN, SnO₂, or acombination thereof; however, the inventive concept is not limitedthereto. The dielectric film 160 may include HfO₂, ZrO₂, Al₂O₃, La₂O₃,Ta₂O₃, Nb₂O₅, CeO₂, TiO₂, GeO₂, or a combination thereof however, theinventive concept is not limited thereto.

The lower electrode LE may be supported by an upper support structureUSS and a lower support structure LSS. The lower support structure LSSmay support a lower portion of the lower electrode LE. The upper supportstructure USS may be apart from the lower support structure LSS in thevertical direction (Z direction) perpendicular to the substrate 110, andsupport an upper portion of the lower electrode LE. For example, theupper support structure USS may not contact the lower support structureLSS.

The upper support structure USS may include an upper support pattern144P and upper concavo-convex structures (i.e., a first upperconcavo-convex structure 146L and a second upper concavo-convexstructure 146H). The upper support pattern 144P may surround an upperportion the lower electrode LE and extend in a horizontal directionparallel with the substrate 110.

A hole 144H through which the plurality of lower electrodes LE pass maybe formed in the upper support pattern 144P. An interior surface of theupper support pattern 144 p exposed by the hole 144H, may contact andsurround an exterior surface of the lower electrode LE. The upperconcavo-convex structures may include the first upper concavo-convexstructure 146L and the second upper concavo-convex structure 146Harranged at a lower surface and an upper surface of the upper supportpattern 144P, respectively. The first upper concavo-convex structure146L and the second upper concavo-convex structure 146H may respectivelyinclude upper convex portions and upper concave portions.

In some embodiments, the first upper concavo-convex structure 146L andthe second upper concavo-convex structure 146H may benano-concavo-convex structures obtained by adjusting a thicknessuniformity in the Z-direction of the upper support pattern 144P. Thenano-concavo-convex structure may be a concavo-convex structure ofseveral nanometers. In some embodiments, the first upper concavo-convexstructure 146L and the second upper concavo-convex structure 146H may benano-concavo-convex structures obtained by adjusting a surface roughnessof the upper support pattern 144P.

In some embodiments, the first upper concavo-convex structure 146L andthe second upper concavo-convex structure 146H may be cluster structures(e.g., an aggregation of structures located in close proximity to eachother) formed on the upper support pattern 144P. As illustrated in FIG.3 , for example, The concavo-convex arrangement of the first upperconcavo-convex structure 146L and the second upper concavo-convexstructure 146H may be uniform. However, in some embodiments, theconcavo-convex arrangement may be irregular (i.e., not uniform).

The upper support pattern 144P, the first upper concavo-convex structure146L, and the second upper concavo-convex structure 146H may include ormay be formed of a silicon carbon nitride film, a silicon nitride filmincluding boron, or a combination thereof. In some embodiments, theupper support pattern 144P, the first upper concavo-convex structure146L, and the second upper concavo-convex structure 146H may include ormay be formed of the same material.

The lower support structure LSS may include a lower support pattern 142Pand lower concavo-convex structures (i.e., a first lower concavo-convexstructure 143L and a second lower concavo-convex structure 143H). Thelower support pattern 142P may extend in a horizontal direction parallelwith the substrate 110. The lower support pattern 142P may be disposedat a level in the Z-direction that is between the substrate 110 and theupper support pattern 144P. The lower support pattern 142P may be incontact with the lower electrode LE.

A hole 142H through which the lower electrode LE passes may be formed inthe lower support pattern 142P. The lower electrode LE may pass throughthe hole 144H formed in the upper support pattern 144P and the hole 142Hformed in the lower support pattern 142P in the vertical direction (Zdirection). An interior surface of the lower support pattern 142Pexposed by the hole 142H, may contact and surround an exterior surfaceof the lower electrode LE.

The lower concavo-convex structures may include the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H arranged at a lower surface and an upper surface of thelower support pattern 142P, respectively. In some embodiments, the firstlower concavo-convex structure 143L and the second lower concavo-convexstructure 143H may be nano-concavo-convex structures obtained byadjusting a thickness uniformity in the Z-direction of the lower supportpattern 142P. The first lower concavo-convex structure 143L and thesecond lower concavo-convex structure 143H may respectively includelower convex portions and lower concave portions.

In some embodiments, the first lower concavo-convex structure 143L andthe second lower concavo-convex structure 143H may benano-concavo-convex structures obtained by adjusting a surface roughnessof the lower support pattern 142P. In some embodiments, the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H may be cluster structures (e.g., an aggregation ofstructures located in close proximity to each other) formed on the lowersupport pattern 142P. As illustrated in FIG. 3 , for example, theconcavo-convex arrangement of the first lower concavo-convex structure143L and the second lower concavo-convex structure 143H may be uniform.However, in some embodiments, the concavo-convex arrangement may beirregular (i.e., not uniform).

The lower support pattern 142P, the first lower concavo-convex structure143L, and the second lower concavo-convex structure 143H may include ormay be formed of a silicon carbon nitride film, a silicon nitride filmincluding boron, or a combination thereof. In some embodiments, thelower support pattern 142P, the first lower concavo-convex structure143L, and the second lower concavo-convex structure 143H may include thesame material.

In some embodiments, the upper support structure USS and the lowersupport structure LSS may include or may be formed of the same material.In an embodiment, the upper support structure USS and the lower supportstructure LSS may include or may be formed of a silicon carbon nitridefilm. In some embodiments, the upper support structure USS and the lowersupport structure LSS may include or may be formed of differentmaterials.

In an embodiment, the upper support structure USS may include or may beformed of a silicon carbon nitride film, and the lower support structureLSS may include or may be formed of a silicon nitride film includingboron. However, according to embodiments of the inventive concept, thematerials included in the upper support structure USS and the lowersupport structure LSS are not limited to the foregoing examples, andvarious changes and modifications may be made within the scope of thetechnical aspects of the inventive concept.

Although the integrated circuit semiconductor device 100 of theembodiment is described as including two support structures, i.e., theupper support structure USS and the lower support structure LSS, moresupport structures may be included in the integrated circuitsemiconductor device 100. As illustrated in FIG. 3 , for example, theupper support structure USS of the integrated circuit semiconductordevice 100 of the embodiment may have a thickness in the Z-directiongreater than that of the lower support structure LSS. However, thethickness of the upper support structure USS of the integrated circuitsemiconductor device 100 may be less than that of the lower supportstructure LSS. However, the thicknesses of the upper support structureUSS and the lower support structure LSS are not limited thereto.

In the integrated circuit semiconductor device 100, a space betweenupper portions of each of the plurality of lower electrodes LE may befilled with the upper support structure USS. In the integrated circuitsemiconductor device 100, a space between lower portions of each of theplurality of lower electrodes LE may be filled with the lower supportstructure LSS. Accordingly, even when a height of the plurality of lowerelectrodes LE is increased, and an aspect ratio becomes relativelygreater to improve the capacitance of the plurality of capacitors CP1,the plurality of lower electrodes LE may extend in a substantiallyperpendicular direction (i.e., Z-direction) with respect to a topsurface of the substrate 110 (extending in the X and Y-directions). Forexample, as a result of the upper support structures USS and the lowersupport structures LSS being disposed between the lower electrodes LE,the lower electrodes LE may not be inclined or fall down.

Through the first upper concavo-convex support structure 146L and thesecond upper concavo-convex support structure 146H included in the uppersupport structure USS and the first lower concavo-convex supportstructure 143L and the second lower concavo-convex support structure143H included in the lower support structure LSS, the integrated circuitsemiconductor device 100 may suppress the occurrence of a bridge byincreasing a surface length between adjacent lower electrodes LE.

FIGS. 4 and 5 are enlarged cross-sectional views for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, FIG. 4 is an enlarged cross-sectional view of a part EN1of FIG. 3 , and FIG. 5 is an enlarged cross-sectional view of the lowersupport structure LSS of FIG. 4 . In the integrated circuitsemiconductor device 100 of FIG. 3 , the lower support structure LSS maybe arranged between the plurality of lower electrodes LE.

The lower support structure LSS may include a lower support pattern 142Pand lower concavo-convex structures (i.e., a first lower concavo-convexstructure 143L and a second lower concavo-convex structure 143H). Thelower support pattern 142P may be in contact with the plurality of lowerelectrodes LE. In some embodiments, the lower support pattern 142P, thefirst lower concavo-convex structure 143L, and the second lowerconcavo-convex structure 143H may include or may be formed of the samematerial.

The lower concavo-convex structures may include the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H arranged at a lower surface and an upper surface of thelower support pattern 142P, respectively. The first lower concavo-convexstructure 143L may include a plurality of first convex portions CV1 anda plurality of first concave portions CA1 arranged between the firstconvex portions CV1. The second lower concavo-convex structure 143H mayinclude a plurality of second convex portions CV2 and a plurality ofsecond concave portions CA2 arranged between the second convex portionsCV2.

In some embodiments, the first lower concavo-convex structure 143L andthe second lower concavo-convex structure 143H may benano-concavo-convex structures obtained by adjusting the thicknessuniformity in the Z-direction or the surface roughness of the lowersupport pattern 142P. For example, the first lower concavo-convexstructure 143L and the second lower concavo-convex structure 143H may beobtained by changing a deposition rate, a deposition gas, or adeposition process parameter of a lower support film 142 (see FIG. 14B),and adjusting the thickness uniformity in the Z-direction or the surfaceroughness of the lower support film 142, when depositing the lowersupport film 142 to form the lower support pattern 142P.

In some embodiments, the first lower concavo-convex structure 143L andthe second lower concavo-convex structure 143H may be cluster structuresformed on the lower support pattern 142P. The arrangement of the firstconvex portions CV1 and the second convex portions CV2 constituting thefirst lower concavo-convex structure 143L and the second lowerconcavo-convex structure 143H as illustrated with reference to FIGS. 4and 5 may be uniform. However, in some embodiments, the arrangement ofthe first convex portions CV1 and the second convex portions CV2 of thefirst lower concavo-convex structure 143L and the second lowerconcavo-convex structure 143H may be irregular (i.e., not uniform).

In some embodiments, the first lower concavo-convex structure 143L andthe second lower concavo-convex structure 143H may have a wave shapehaving valleys and ridges. In some embodiments, the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H may have an elliptical cross-section.

When the integrated circuit semiconductor device 100 of FIG. 3 includesthe first lower concavo-convex structure 143L and the second lowerconcavo-convex structure 143H, the occurrence of a bridge between thelower electrodes LE may be suppressed by increasing a surface length L2of the lower support structure LSS as illustrated in FIG. 5 . Forexample, by increasing the surface length L2, the distance that anelectron must travel between the adjacent lower electrodes LE isincreased. Therefore, a bridge between the lower electrodes LE may besuppressed.

For example, the reference symbol L1 in FIG. 5 may denote a surfacelength of the lower support structure without the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H. For example, if the lower support structure LSS did notinclude the first lower concavo-convex structure 143L and the secondlower concavo-convex structure 143H, the top and bottom surfaces(extending in the X and Y-directions) of the lower support structurewould be substantially planar. As such, the surface length in theX-direction of the top surface of the lower support structure LSS andthe bottom surface of the lower support structure LSS would each beequal to L1. Moreover, L1 is equal to the distance between therespective lower electrodes LE between which the lower support structureLSS is disposed. Accordingly, L1 may also denote a distance between thelower electrodes LE as illustrated in FIG. 5 .

The reference symbol L2 in FIG. 5 may denote the surface length in theX-direction of the lower support structure LSS between the lowerelectrodes LE. As a result of the of the inclusion of the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H, L2 is greater than L1. Accordingly, the integratedcircuit semiconductor device 100 of FIG. 3 may suppress the occurrenceof a bridge between the lower electrodes LE by increasing the surfacelength L2 of the lower support structure LSS between the lowerelectrodes LE to be greater than the distance L1 between the lowerelectrodes LE.

In FIGS. 4 and 5 , the inventive concept takes an example of the lowersupport structure LSS including the lower support pattern 142P, thefirst lower concavo-convex structure 143L, and the second lowerconcavo-convex structure 143H for convenience; however, the inventiveconcept may also be applied to the upper support structure USS includingthe upper support pattern 144P, the first upper concavo-convex structure146L, and the second upper concavo-convex structure 146H. Hereinafter,the technical aspects of the inventive concept are described by takingthe lower support structure LSS as an example for convenience.

FIGS. 6 and 7 are enlarged cross-sectional views for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, a lower support structure LSS-1 of FIGS. 6 and 7 may beanother embodiment of the lower support structure LSS of FIGS. 4 and 5 .FIG. 7 is an enlarged cross-sectional view of the lower supportstructure LSS-1 of FIG. 6 . In FIGS. 6 and 7 , reference numeralsidentical or similar to the reference numerals in FIGS. 4 and 5 denoteidentical or similar elements.

In the integrated circuit semiconductor device 100 of FIG. 3 , the lowersupport structure LSS-1 may be arranged between the plurality of lowerelectrodes LE. The lower support structure LSS-1 may include a lowersupport pattern 142P-1 and lower concavo-convex structures (i.e., afirst lower concavo-convex structure 143L-1 and a second lowerconcavo-convex structure 143H-1). The lower support pattern 142P-1, thefirst lower concavo-convex structure 143L-1, and the second lowerconcavo-convex structure 143H-1 may be structurally distinguished fromeach other. A lower surface and an upper surface of the lower supportpattern 142P-1 may be a flat (e.g., substantially planar) surfaceparallel with the substrate 110 of FIG. 3 .

The lower concavo-convex structures may include the first lowerconcavo-convex structure 143L-1 and the second lower concavo-convexstructure 143H-1 arranged at a lower surface and an upper surface of thelower support pattern 142P-1, respectively. The first lowerconcavo-convex structure 143L-1 may include a plurality of first convexportions CV1-1 and a plurality of first concave portions CA1-1 arrangedbetween the first convex portions CV1-1. The second lower concavo-convexstructure 143H-1 may include a plurality of second convex portions CV2-1and a plurality of second concave portions CA2-1 arranged between thesecond convex portions CV2-1.

In some embodiments, the first lower concavo-convex structure 143L-1 andthe second lower concavo-convex structure 143H-1 may be clusterstructures formed on the lower support pattern 142P-1. As illustrated inFIGS. 6 and 7 , the arrangement of the first convex portions CV1-1 andthe second convex portions CV2-1 constituting the first lowerconcavo-convex structure 143L-1 and the second lower concavo-convexstructure 143H-1 may be uniform. However, in some embodiments, thearrangement of the first convex portions CV1-1 and the second convexportions CV2-1 of the first lower concavo-convex structure 143L-1 andthe second lower concavo-convex structure 143H-1 may be irregular (i.e.,not uniform).

In some embodiments, the lower support pattern 142P-1, the first lowerconcavo-convex structure 143L-1, and the second lower concavo-convexstructure 143H-1 may include or may be formed of different materials. Insome embodiment, when the lower support pattern 142P-1, the first lowerconcavo-convex structure 143L-1, and the second lower concavo-convexstructure 143H-1 include or are formed of different materials, the firstlower concavo-convex structure 143L-1 and the second lowerconcavo-convex structure 143H-1 may be formed by controlling an etchingspeed of a material included in the first lower concavo-convex structure143L-1 and the second lower concavo-convex structure 143H-1.

In some embodiments, the first lower concavo-convex structure 143L-1 andthe second lower concavo-convex structure 143H-1 may benano-concavo-convex structures obtained by a lithography processperformed on the lower support pattern 142P-1. For example, the lowerconcavo-convex structures may include the first lower concavo-convexstructure 143L-1 and the second lower concavo-convex structure 143H-1obtained by a lithography process performed on the lower support pattern142P-1.

The lithography process may be a photolithography process usingphotoresist or a block copolymer lithography using block copolymer.

In some embodiments, the first lower concavo-convex structure 143L-1 andthe second lower concavo-convex structure 143H-1 may have a wave shapehaving valleys and ridges. In some embodiments, the first lowerconcavo-convex structure 143L-1 and the second lower concavo-convexstructure 143H-1 may have an elliptical cross-section.

When the integrated circuit semiconductor device 100 of FIG. 3 includesthe first lower concavo-convex structure 143L-1 and the second lowerconcavo-convex structure 143H-1, the occurrence of a bridge between thelower electrodes LE may be suppressed by increasing a surface length L2between the lower electrodes LE as illustrated in FIG. 7 .

FIG. 8 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, a lower support structure LSS-2 of FIG. 8 may be anotherembodiment of the lower support structure LSS of FIGS. 4 and 5 . In FIG.8 , reference numerals identical or similar to the reference numerals inFIGS. 4 and 5 denote identical or similar elements.

The lower support structure LSS-2 may include a lower support pattern142P-2 and lower concavo-convex structures (i.e., a first lowerconcavo-convex structure 143L-2 and a second lower concavo-convexstructure 143H-2). The lower support pattern 142P-2, the first lowerconcavo-convex structure 143L-2, and the second lower concavo-convexstructure 143H-2 may be structurally distinguished from each other. Alower surface P1 and an upper surface P2 of the lower support pattern142P-2 may be a flat (e.g., substantially planar) surface.

In some embodiments, the lower support pattern 142P-2, the first lowerconcavo-convex structure 143L-2, and the second lower concavo-convexstructure 143H-2 may include or may be formed of the same material. Insome embodiments, the lower support pattern 142P-2, the first lowerconcavo-convex structure 143L-2, and the second lower concavo-convexstructure 143H-2 may include or may be formed of different materials.

The lower concavo-convex structures may include the first lowerconcavo-convex structure 143L-2 and the second lower concavo-convexstructure 143H-2 arranged at a lower surface and an upper surface of thelower support pattern 142P-2, respectively. The first lowerconcavo-convex structure 143L-2 may include a plurality of first convexportions CV1-2 and a plurality of first concave portions CA1-2 arrangedbetween the first convex portions CV1-2. The second lower concavo-convexstructure 143H-2 may include a plurality of second convex portions CV2-2and a plurality of second concave portions CA2-2 arranged between thesecond convex portions CV2-2.

In some embodiments, the first lower concavo-convex structure 143L-2 andthe second lower concavo-convex structure 143H-2 may benano-concavo-convex structures obtained by a lithography processperformed on the lower support pattern 142P-2. For example, the lowerconcavo-convex structures may include the first lower concavo-convexstructure 143L-2 obtained by a lithography process on a mold film andthe second lower concavo-convex structure 143H-2 obtained by alithography process performed on the lower support pattern 142P-2.

The lithography process may be a photolithography process usingphotoresist or a block copolymer lithography using block copolymer.

In some embodiments, the first lower concavo-convex structure 143L-2 andthe second lower concavo-convex structure 143H-2 may have a stair shape.In some embodiments, the first lower concavo-convex structure 143L-2 andthe second lower concavo-convex structure 143H-2 may have a rectangularcross-section. In some embodiments, the first lower concavo-convexstructure 143L-2 and the second lower concavo-convex structure 143H-2may have a wave shape having ridges and valleys, unlike in FIG. 8 .

When the integrated circuit semiconductor device 100 of FIG. 3 includesthe first lower concavo-convex structure 143L-2 and the second lowerconcavo-convex structure 143H-2, the occurrence of a bridge between thelower electrodes LE of FIG. 3 may be suppressed by increasing a surfacelength of the lower support structure LSS-2 between the lower electrodesLE of FIG. 3 .

FIG. 9 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, a lower support structure LSS-3 may be another embodimentof the lower support structure LSS of FIGS. 4 and 5 . The lower supportstructure LSS-3 of FIG. 9 may be identical to the lower supportstructure LSS-2 of FIG. 8 except for a corner portion CR of a lowersupport pattern 142P-3. In FIG. 9 , reference numerals identical orsimilar to the reference numerals in FIGS. 4, 5, and 8 denote identicalor similar elements.

The lower support structure LSS-3 may include the lower support pattern142P-3 and lower concavo-convex structures (i.e., a first lowerconcavo-convex structure 143L-2 and a second lower concavo-convexstructure 143H-2). The lower support pattern 142P-3, the first lowerconcavo-convex structure 143L-2, and the second lower concavo-convexstructure 143H-2 may be structurally distinguished from each other.

In some embodiments, the lower support pattern 142P-3, the first lowerconcavo-convex structure 143L-2, and the second lower concavo-convexstructure 143H-2 may include or may be formed of the same material. Insome embodiments, the lower support pattern 142P-3, the first lowerconcavo-convex structure 143L-2, and the second lower concavo-convexstructure 143H-2 may include or may be formed of different materials.

A lower surface P1 and an upper surface P2 of the lower support pattern142P-3 may be a flat (e.g., substantially planar) surface. The cornerportion CR of the lower support pattern 142P-3 may have a curvedsurface. The corner portion CR of the lower support pattern 142P-3 maybe in contact with the lower electrode LE (see FIG. 4 ). The cornerportion CR of the lower support pattern 142P-3 may have a curved surfacehaving a thickness tapering off towards the lower electrode LE (see FIG.4 ).

When a curved surface is formed at the corner portion CR of the lowersupport pattern 142P-3, the lower support structure LSS-3 may suppressthe occurrence of a bridge between lower electrodes LE (see FIG. 3 ) byincreasing a surface length of the lower support structure LSS-3 betweenthe lower electrodes LE (see FIG. 3 ) through inclusion of the lowerconcavo-convex structures and the corner portion CR. The reference L3may denote the length of the corner portion CR.

The lower support structure LSS-3 may include the first lowerconcavo-convex structure 143L-2 and the second lower concavo-convexstructure 143H-2. The lower concavo-convex structures may include thefirst lower concavo-convex structure 143L-2 and the second lowerconcavo-convex structure 143H-2 arranged at a lower surface and an uppersurface of the lower support pattern 142P-2, respectively. As the firstlower concavo-convex structure 143L-2 and the second lowerconcavo-convex structure 143H-2 have been described above, descriptionsthereon are omitted hereinafter.

When the lower support structure LSS-3 includes the curved surface ofthe corner portion CR of the lower support pattern 142P-3, and the firstlower concavo-convex structure 143L-2, and the second lowerconcavo-convex structure 143H-2 on the lower support pattern 142P-3, asurface length of the lower support structure LSS-3 between the lowerelectrodes LE (see FIG. 3 ) may be further increased to suppress theoccurrence of a bridge between the lower electrodes LE (see FIG. 3 ).

FIG. 10 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, a lower support structure LSS-4 may be another embodimentof the lower support structure LSS of FIGS. 4 and 5 . The lower supportstructure LSS-4 may be identical to the lower support structure LSS-2 ofFIG. 8 except for the structure of lower concavo-convex structures(i.e., a first lower concavo-convex structure 143L-3 and a second lowerconcavo-convex structure 143H-3). In FIG. 10 , reference numeralsidentical or similar to the reference numerals in FIGS. 4, 5, and 8denote identical or similar elements.

The lower support structure LSS-4 may include the lower support pattern142P-2, the first lower concavo-convex structure 143L-3, and the secondlower concavo-convex structure 143H-3. The lower support pattern 142P-2,the first lower concavo-convex structure 143L-3, and the second lowerconcavo-convex structure 143H-3 may be structurally distinguished fromeach other. A lower surface P1 and an upper surface P2 of the lowersupport pattern 142P-2 may be a flat (e.g., substantially planar)surface.

In some embodiments, the lower support pattern 142P-2, the first lowerconcavo-convex structure 143L-3, and the second lower concavo-convexstructure 143H-3 may include or may be formed of the same material. Insome embodiments, the lower support pattern 142P-2, the first lowerconcavo-convex structure 143L-3, and the second lower concavo-convexstructure 143H-3 may include or may be formed of different materials.

The lower concavo-convex structures may include the first lowerconcavo-convex structure 143L-3 and the second lower concavo-convexstructure 143H-3 arranged at a lower surface and an upper surface of thelower support pattern 142P-2, respectively. The first lowerconcavo-convex structure 143L-3 may include a plurality of first convexportions CV1-3 and a plurality of first concave portions CA1-3 arrangedbetween the first convex portions CV1-3. The second lower concavo-convexstructure 143H-3 may include a plurality of second convex portions CV2-3and a plurality of second concave portions CA2-3 arranged between thesecond convex portions CV2-3.

In some embodiments, the first lower concavo-convex structure 143L-3 andthe second lower concavo-convex structure 143H-3 may benano-concavo-convex structures obtained by a lithography processperformed on the lower support pattern 142P-2. For example, the lowerconcavo-convex structures may include the first lower concavo-convexstructure 143L-3 obtained by a lithography process on a mold film andthe second lower concavo-convex structure 143H-3 obtained by alithography process performed on the lower support pattern 142P-2.

The lithography process may be a photolithography process usingphotoresist or a block copolymer lithography using block copolymer.

In some embodiments, the first convex portions CV1-3 and the secondconvex portions CV2-3 constituting the first lower concavo-convexstructure 143L-3 and the second lower concavo-convex structure 143H-3may have a triangular shaped cross-section. In some embodiments, thefirst convex portions CV1-3 and the second convex portions CV2-3constituting the first lower concavo-convex structure 143L-3 and thesecond lower concavo-convex structure 143H-3 may have a diamond shapedcross-section, unlike in FIG. 10 .

When the lower support structure LSS-4 includes the first lowerconcavo-convex structure 143L-2 and the second lower concavo-convexstructure 143H-2, the occurrence of a bridge between the lowerelectrodes LE of FIG. 3 may be suppressed by increasing a surface lengthof the lower support structure LSS-4 between the lower electrodes LE ofFIG. 3 .

FIG. 11 is an enlarged cross-sectional view for explaining a lowersupport structure of an integrated circuit semiconductor deviceaccording to an embodiment.

Specifically, a lower support structure LSS-5 may be another embodimentof the lower support structure LSS of FIGS. 4 and 5 . The lower supportstructure LSS-5 may be identical to the lower support structure LSS-4 ofFIG. 10 except for the corner portion CR of the lower support pattern142P-3. In FIG. 11 , reference numerals identical or similar to thereference numerals in FIGS. 4, 5, and 10 denote identical or similarelements.

The lower support structure LSS-5 may include the lower support pattern142P-3 and lower concavo-convex structures (i.e., the first lowerconcavo-convex structure 143L-3 and the second lower concavo-convexstructure 143H-3). The lower support pattern 142P-3, the first lowerconcavo-convex structure 143L-3, and the second lower concavo-convexstructure 143H-3 may be structurally distinguished from each other.

In some embodiments, the lower support pattern 142P-3, the first lowerconcavo-convex structure 143L-3, and the second lower concavo-convexstructure 143H-3 may include or may be formed of the same material. Insome embodiments, the lower support pattern 142P-3, the first lowerconcavo-convex structure 143L-3, and the second lower concavo-convexstructure 143H-3 may include or may be formed of different materials.

A lower surface P1 and an upper surface P2 of the lower support pattern142P-3 may be a flat (e.g., substantially planar) surface. The cornerportion CR of the lower support pattern 142P-3 may have a curvedsurface. The corner portion CR of the lower support pattern 142P-3 maybe in contact with the lower electrode LE (see FIG. 4 ). The cornerportion CR of the lower support pattern 142P-3 may have a curved surfacehaving a thickness tapering off towards the lower electrode LE (see FIG.4 ).

When a curved surface is formed at the corner portion CR of the lowersupport pattern 142P-3, the lower support structure LSS-5 may suppressthe occurrence of a bridge between lower electrodes LE (see FIG. 3 ) byincreasing a surface length of the lower support structure LSS-5 betweenthe lower electrodes LE (see FIG. 3 ) through inclusion of the lowerconcavo-convex structures and the corner portion CR. The reference L3may denote the length of the corner portion CR.

The lower support structure LSS-5 may include the first lowerconcavo-convex structure 143L-3 and the second lower concavo-convexstructure 143H-3. The lower concavo-convex structures may include thefirst lower concavo-convex structure 143L-3 and the second lowerconcavo-convex structure 143H-3 arranged at a lower surface and an uppersurface of the lower support pattern 142P-3, respectively. As the firstlower concavo-convex structure 143L-3 and the second lowerconcavo-convex structure 143H-3 have been described above, descriptionsthereon are omitted hereinafter.

When the lower support structure LSS-5 includes the curved surface ofthe corner portion CR of the lower support pattern 142P-3, the firstlower concavo-convex structure 143L-3, and the second lowerconcavo-convex structure 143H-3 on the lower support pattern 142P-3, asurface length of the lower support structure LSS-3 between the lowerelectrodes LE (see FIG. 3 ) may be further increased to suppress theoccurrence of a bridge between the lower electrodes LE (see FIG. 3 ).

FIG. 12 is a plan view showing some components of an integrated circuitsemiconductor device according to an embodiment, and FIG. 13 is across-sectional view schematically showing some components of across-section taken along the 2X-2X′ line of FIG. 12 .

Specifically, an integrated circuit semiconductor device 100-1 may beidentical to the integrated circuit semiconductor device 100 of FIGS. 2and 3 except for additional holes (i.e., lower additional holes LH andupper additional holes UH) formed between the lower electrodes LE. InFIGS. 12 and 13 , reference numerals identical or similar to thereference numerals in FIGS. 2 and 3 denote identical or similarelements.

The integrated circuit semiconductor device 100-1 may include the lowerelectrode LE supported by the upper support structure USS and the lowersupport structure LSS. A plurality of holes 142H and a plurality oflower additional holes LH through which the plurality of lowerelectrodes LE pass may be formed in the lower support structure LSS,i.e., in the lower support pattern 142P. The plurality of holes 142H andthe plurality of lower additional holes LH may be arranged on the sameplane.

A plurality of holes 144H and a plurality of upper additional holes UHthrough which the plurality of lower electrodes LE pass may be formed inthe upper support structure USS, i.e., in the upper support pattern144P. The plurality of holes 144H and the plurality of upper additionalholes UH may be arranged on the same plane.

FIG. 12 illustrates that each of the plurality of upper additional holesUH and the plurality of lower additional holes LH has a roughly diamondshaped plan view in which four adjacent lower electrodes LE are eachvertex; however, the plan view may have a shape of polygon, for example,a triangle and a square. A plan view of each of the upper additionalhole UH and the lower additional hole LH is not limited to thedescription of FIG. 12 , and various changes and modifications may bemade within the scope of the technical aspects of the inventive concept.

The integrated circuit semiconductor device 100-1 may include the lowersupport structure LSS and the lower additional holes LH, and may includethe upper support structure USS and the upper additional holes UH. Thelower support structure LSS does not support all portion of theplurality of lower electrodes LE. The upper support structure USS doesnot support all portion of the plurality of lower electrodes LE.

FIGS. 14A to 14F are cross-sectional views illustrating a method ofmanufacturing an integrated circuit semiconductor device, according toan embodiment.

Specifically, FIGS. 14A to 14F are diagrams for explaining a method ofmanufacturing the integrated circuit semiconductor device 100 of FIGS. 2and 3 . Like reference numerals in FIGS. 14A to 14F denote like elementsin FIGS. 2 and 3 , and thus their description will be omitted.

With reference to FIG. 14A, the lower structure 120 and the conductivearea 124 passing through the lower structure 120 and connected to theactive area AC may be formed on the substrate 110 of which the activearea AC is defined by the device separation area 112. Then, aninsulating film 126 to cover the lower structure 120 and the conductivearea 124 may be formed.

The insulating film 126 may be used as an etch stop layer in subsequentprocesses. The insulating film 126 may include an insulator having anetch selectivity with respect to the lower structure 120. In someembodiments, the insulating film 126 may include or may be formed of asilicon nitride film, a silicon carbon nitride film, a silicon nitridefilm including boron, or a combination thereof.

With reference to FIG. 14B, a mold structure MST may be formed on theinsulating film 126. The mold structure MST may include a plurality ofmold layers and a plurality of support layers. For example, the moldstructure MST may include a first mold film 132, a lower support film142 having lower concavo-convex structures 143L′ and 143H′, a secondmold film 134, and an upper support film 144 having upper concavo-convexstructures 146L′ and 146H′, which are stacked in this stated order onthe insulating film 126.

Each of the first mold film 132 and the second mold film 134 may includea material having a relatively high etch rate with respect to etchantsincluding ammonium fluoride (NH₄F), hydrofluoric acid (HF), and water sothat the material may be removed through a lift-off process by theetchants. In some embodiments, each of the first mold film 132 and thesecond mold film 134 may include or may be formed of an oxide film, anitride film, or a combination thereof. However, the material includedin the first mold film 132 and the second mold film 134 is not limitedto the foregoing, and various changes and modifications may be madewithin the scope of the technical aspects of the inventive concept.Furthermore, the stacking order of the mold structure MST is not limitedto the description of FIG. 14B, and various changes and modificationsmay be made within the scope of the technical aspects of the inventiveconcept.

Each of the lower support film 142 having the lower concavo-convexstructures 143L′ and 143H′ and the upper support film 144 having theupper concavo-convex structures 146L′ and 146H′ may include or may beformed of a silicon carbon nitride film, a silicon nitride filmincluding boron, or a combination thereof. In some embodiments, thelower support film 142 having the lower concavo-convex structures 143L′and 143H′ and the upper support film 144 having the upper concavo-convexstructures 146L′ and 146H′ may include or may be formed of the samematerial. In some embodiments, the lower support film 142 having thelower concavo-convex structures 143L′ and 143H′ and the upper supportfilm 144 having the upper concavo-convex structures 146L′ and 146H′ mayinclude or may be formed of different materials.

In some embodiments, the lower support film 142 having the lowerconcavo-convex structures 143L′ and 143H′ and the upper support film 144having the upper concavo-convex structures 146L′ and 146H′ mayrespectively include or may be formed of silicon carbon nitride films.In other embodiments, the lower support film 142 having the lowerconcavo-convex structures 143L′ and 143H′ may include or may be formedof a silicon carbon nitride film, and the upper support film 144 havingthe upper concavo-convex structures 146L′ and 146H′ may include or maybe formed of a silicon nitride film including boron. However, accordingto embodiments of the inventive concept, the material included in thelower support film 142 having the lower concavo-convex structures 143L′and 143H′ and the upper support film 144 having the upper concavo-convexstructures 146L′ and 146H′ is not limited to the foregoing, and variouschanges and modifications may be made within the scope of the technicalaspects of the inventive concept.

In some embodiments, the lower concavo-convex structures 143L′ and 143H′may be nano-concavo-convex structures obtained by adjusting a thicknessuniformity of the lower support film 142. In some embodiments, the lowerconcavo-convex structures 143L′ and 143H′ may be obtained by changing adeposition rate, a deposition gas, or a deposition process parameter ofthe lower support film 142, and adjusting the thickness uniformity ofthe lower support film 142, when depositing the lower support film 142on the first mold film 132.

The upper concavo-convex structures 146L′ and 146H′ may benano-concavo-convex structures obtained by adjusting a thicknessuniformity of the upper support film 144. In some embodiments, the upperconcavo-convex structures 146L′ and 146H′ may be obtained by changing adeposition rate, a deposition gas, or a deposition process parameter ofthe upper support film 144, and adjusting the thickness uniformity ofthe upper support film 144, when depositing the upper support film 144on the second mold film 134.

With reference to FIG. 14C, after forming a mask pattern MP on the moldstructure MST, a plurality of holes BH may be formed by anisotropicallyetching the mold structure MST using the mask pattern MP as an etchingmask and the insulating film 126 as an etch stop layer. The mask patternMP may include or may be formed of a nitride film, an oxide film, apolysilicon film, a photoresist layer, or a combination thereof.

As a result, a mold structure pattern MSP defining the plurality ofholes BH may be obtained. The mold structure pattern MSP may include afirst mold pattern 132P, the lower support pattern 142P having the firstlower concavo-convex structure 143L and the second lower concavo-convexstructure 143H, a second mold pattern 134P, and the upper supportpattern 144P having the first upper concavo-convex structure 146L andthe second upper concavo-convex structure 146H.

A process of forming the plurality of holes BH may further includewet-processing a result of anisotropic-etching of the mold structureMST. When performing the anisotropic-etching and wet-processing of theresult, the insulating film 126 may also be partially etched, and theinsulating pattern 126P having the plurality of openings 126H exposingthe plurality of conductive areas 124 may be obtained. In an exampleprocess of wet-processing the result of anisotropic-etching, an enchantincluding diluted sulfuric acid peroxide solution may be used.

With reference to FIG. 14D, after removing the mask pattern MP, on aresult of the removal illustrated in FIG. 14C, a conductive layer 150may be formed. The conductive layer 150 may be formed to fill theplurality of holes BH. The conductive layer 150 may include a metalfilm, a conductive metal oxide film, a conductive metal nitride film, aconductive metal oxynitride film, or a combination thereof.

In some embodiments, the conductive layer 150 may include or may beformed of Ti, Ti oxide, Ti nitride, Ti oxynitride, Co, Co oxide, Conitride, Co oxynitride, Nb, Nb oxide, Nb nitride, Nb oxynitride, Sn, Snoxide, Sn nitride, Sn oxynitride, or a combination thereof. For example,the conductive layer 150 may include or may be formed of TiN, CoN, NbN,SnO₂, or a combination thereof; however, the inventive concept is notlimited thereto. To form the conductive layer 150, chemical vapordeposition (CVD), plasma enhanced CVD (PECVD), metal organic CVD(MOCVD), or atomic layer deposition (ALD) may be used.

With reference to FIG. 14E, the conductive layer 150 may be partiallyremoved by using an etchback process or a chemical mechanical polishing(CMP) process until an upper surface of the second upper concavo-convexstructure 146H, which is the uppermost layer of the mold structurepattern MSP, is exposed in the result described with reference to FIG.14D. As a result, the plurality of lower electrodes LE formed ofremaining portions inside the plurality of holes BH (see FIG. 14D) inthe conductive layer 150 may be obtained.

With reference to FIG. 14F, the first mold pattern 132P and the secondmold pattern 134P may be removed through a wet process. An enchantincluding ammonium fluoride (NH₄F), hydrofluoric acid (HF), and watermay be used in the process of removing the first mold pattern 132P andthe second mold pattern 134P through the wet process. After removing thefirst mold pattern 132P and the second mold pattern 134P, lateral wallsof the plurality of lower electrodes LE may be exposed, and in a spacebetween the plurality of lower electrodes LE, the upper support pattern144P, the first upper concavo-convex structure 146L, the second upperconcavo-convex structure 146H, the lower support pattern 142P, the firstlower concavo-convex structure 143L, and the second lower concavo-convexstructure 143H may remain.

Accordingly, the upper support pattern 144P, the first upperconcavo-convex structure 146L, and the second upper concavo-convexstructure 146H may be the upper support structure USS, and the lowersupport pattern 142P, the first lower concavo-convex structure 143L, andthe second lower concavo-convex structure 143H may be the lower supportstructure LSS.

Then, the dielectric film 160 to cover exposed surfaces of the lowerelectrodes LE may be formed. The ALD process may be used to form thedielectric film 160. The dielectric film 160 may include or may beformed of HfO₂, ZrO₂, Al₂O₃, La₂O₃, Ta₂O₃, Nb₂O₅, CeO₂, TiO₂, GeO₂, or acombination thereof; however, the inventive concept is not limitedthereto.

Thereafter, as illustrated in FIG. 3 , by forming the upper electrode UEto cover the dielectric film 160, the integrated circuit semiconductordevice 100 including the capacitor CP1 may be manufactured. To form anupper electrode 170, the processes of CVD, MOCVD, PVD, or ALD may beused.

FIGS. 15A and 15B are cross-sectional views illustrating a method ofmanufacturing an integrated circuit semiconductor device, according toan embodiment.

Specifically, FIGS. 15A and 15B are diagrams for explaining a method ofmanufacturing the integrated circuit semiconductor device 100-1 of FIGS.12 and 13 . Like reference numerals in FIGS. 15A and 15B denote likeelements in FIGS. 12 and 13 , and thus their description will beomitted. The method of manufacturing the integrated circuitsemiconductor device 100-1 of FIGS. 12 and 13 may include themanufacturing method of FIGS. 14A to 14E.

With reference to FIG. 15A, after performing the manufacturing processof FIG. 14E, the upper support pattern 144P having the first upperconcavo-convex structure 146L and the second upper concavo-convexstructure 146H may be partially removed to form a plurality of upperholes UH, and through the plurality of upper holes UH, the second moldpattern 134P may be wet-removed.

Then, the lower support pattern 142P having the first lowerconcavo-convex structure 143L and the second lower concavo-convexstructure 143H exposed through the plurality of upper holes UH may bepartially removed to form a plurality of lower holes LH, and bywet-removing the first mold pattern 132P through the plurality of lowerholes LH, an upper surface of the insulating pattern 126P may beexposed. A plan view of each of the plurality of upper holes UH and theplurality of lower holes LH may be as illustrated in FIG. 12 .

The lateral walls of the plurality of lower electrodes LE in the upperhole UH and the lower hole LH and the lateral walls of the lower supportpattern 142P having the first lower concavo-convex structure 143L andthe second lower concavo-convex structure 143H and the upper supportpattern 144P having the first upper concavo-convex structure 146L andthe second upper concavo-convex structure 146H may be exposed.

Furthermore, in a space between the plurality of lower electrodes LE,the upper support pattern 144P, the first upper concavo-convex structure146L, the second upper concavo-convex structure 146H, the lower supportpattern 142P, the first lower concavo-convex structure 143L and thesecond lower concavo-convex structure 143H may remain. The upper supportpattern 144P, the first upper concavo-convex structure 146L, and thesecond upper concavo-convex structure 146H may be the upper supportstructure USS, and the lower support pattern 142P, the first lowerconcavo-convex structure 143L, and the second lower concavo-convexstructure 143H may be the lower support structure LSS.

With reference to FIG. 15B, the dielectric film 160 to cover exposedsurfaces of the lower electrode LE illustrated in FIG. 15A may beformed. The ALD process may be used to form the dielectric film 160. Thedielectric film 160 may include or may be formed of HfO₂, ZrO₂, Al₂O₃,La₂O₃, Ta₂O₃, Nb₂O₅, CeO₂, TiO₂, GeO₂, or a combination thereof;however, the inventive concept is not limited thereto.

Thereafter, as illustrated in FIG. 13 , by forming the upper electrodeUE to cover the dielectric film 160, the integrated circuitsemiconductor device 100-1 including the capacitor CP1 may bemanufactured. To form an upper electrode 170, the processes of CVD,MOCVD, PVD, or ALD may be used.

FIG. 16 is a plan view of a memory module including an integratedcircuit semiconductor device according to the technical aspects of theinventive concept.

Specifically, a memory module 1000 may include a printed circuit board1100 and a plurality of semiconductor packages 1200. The plurality ofsemiconductor packages 1200 may include the integrated circuitsemiconductor device 100 or 100-1 according to embodiments of thetechnical aspects of the inventive concept.

The memory module 1000 according to the technical aspects of theinventive concept may be a single in-lined memory module (SIMM) havingthe plurality of semiconductor packages 1200 mounted on only one side ofa printed circuit board, or a dual in-lined memory module (DIMM) havingthe plurality of semiconductor packages 1200 arranged on both sides.Furthermore, the memory module 1000 according to the technical aspectsof the inventive concept may be a fully buffered DIMM (FBDIMM) having anadvanced memory buffer (AMB) configured to provide a signal from theoutside to each of the plurality of semiconductor packages 1200.

FIG. 17 is a schematic diagram of a memory card including an integratedcircuit semiconductor device according to the technical aspects of theinventive concept.

Specifically, a memory card 2000 may be arranged so that a controller2100 and a memory 2200 may exchange an electronic signal. For example,the memory 2200 may transmit data in response to an instruction from thecontroller 2100.

The memory 2200 may include the integrated circuit semiconductor device100 or 100-1 according to embodiments of the technical aspects of theinventive concept. The memory card 2000 may constitute various types ofmemory cards, for example, a memory stick card, a smart media (SM) card,a secure digital (SD) card, a mini-SD card, a multimedia card (MMC),etc.

FIG. 18 is a schematic diagram of a system including an integratedcircuit semiconductor device according to the technical aspects of theinventive concept.

Specifically, in a system 3000, a processor 3100, a memory 3200, and aninput/output device 3300 may perform mutual data communication by usinga bus 3400. The memory 3200 of the system 3000 may include random accessmemory (RAM) and read only memory (ROM). Furthermore, the system 3000may include a peripheral device 3500, such as a floppy disk drive and acompact disk (CD) ROM drive.

The memory 3200 may include the integrated circuit semiconductor device100 or 100-1 according to embodiments of the technical aspects of theinventive concept. The memory 3200 may store codes and data foroperations of the processor 3100. The system 3000 may be used in amobile phone, an MP3 player, a navigation, a portable multimedia player(PMP), a solid state disk (SSD), or household appliances.

While the inventive concept has been particularly shown and describedwith reference to embodiments thereof, it will be understood thatvarious changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

What is claimed is:
 1. An integrated circuit semiconductor devicecomprising: a lower electrode formed on a substrate extending in a firstdirection and a second direction perpendicular to the first direction;and a support structure supporting the lower electrode, wherein thesupport structure includes a support pattern surrounding the lowerelectrode, extending in the first direction and the second direction,and having a first hole through which the lower electrode passes; and aconcavo-convex structure having at a surface of the support pattern aplurality of convex portions extending in a third directionperpendicular to the first direction and the second direction, and aplurality of concave portions arranged between the convex portions. 2.The integrated circuit semiconductor device of claim 1, wherein thesupport structure comprises a lower support structure supporting a lowerportion of the lower electrode, and an upper support structure spacedapart from the lower support structure in the third direction andsupporting an upper portion of the lower electrode.
 3. The integratedcircuit semiconductor device of claim 1, wherein the support structurefurther comprises a second hole passing through the support pattern andin a plan view, the second hole has a polygonal shape connectingadjacent lower electrodes.
 4. The integrated circuit semiconductordevice of claim 1, wherein the support pattern and the concavo-convexstructure include the same material.
 5. The integrated circuitsemiconductor device of claim 1, wherein the concavo-convex structure isa nano-concavo-convex structure formed on the support pattern.
 6. Theintegrated circuit semiconductor device of claim 1, wherein the supportpattern and the concavo-convex structure include different materials. 7.The integrated circuit semiconductor device of claim 1, wherein thesupport pattern and the concavo-convex structure include a siliconcarbon nitride film, a silicon nitride film including boron, or acombination thereof.
 8. The integrated circuit semiconductor device ofclaim 1, wherein the concavo-convex structure comprises a firstconcavo-convex structure formed at a first surface of the supportpattern and a second concavo-convex structure formed at a second surfaceof the support pattern opposite to the first surface of the supportpattern.
 9. The integrated circuit semiconductor device of claim 1,wherein the concavo-convex structure has a wave shape or a stair shape.10. The integrated circuit semiconductor device of claim 1, wherein across-section of the convex portions constituting the concavo-convexstructure has a triangular, rectangular, or elliptical shape.
 11. Theintegrated circuit semiconductor device of claim 1, wherein the supportpattern includes a corner portion in contact with the lower electrode,and the corner portion of the support pattern has a curved surfacehaving a thickness tapering off towards the lower electrode.
 12. Anintegrated circuit semiconductor device comprising: a plurality of lowerelectrodes spaced apart from each other on a substrate extending in afirst direction and a second direction perpendicular to the firstdirection; a support pattern extending in the first direction and thesecond direction and having a plurality of first holes through which theplurality of lower electrodes pass; and a concavo-convex structurehaving at a surface of the support pattern a plurality of convexportions extending in a third direction perpendicular to the firstdirection and the second direction, and a plurality of concave portionsarranged between the convex portions.
 13. The integrated circuitsemiconductor device of claim 12, wherein the concavo-convex structureincludes a cluster structure formed on a surface of the support pattern.14. The integrated circuit semiconductor device of claim 12, wherein theconcavo-convex structure includes a nano-concavo-convex structure formedon the support pattern.
 15. The integrated circuit semiconductor deviceof claim 12, wherein the surface of the support pattern is a flatsurface extending in the first direction and the second direction. 16.The integrated circuit semiconductor device of claim 12, wherein asecond hole passing through the support pattern is further formedbetween the plurality of lower electrodes, and in a plan view, thesecond hole has a polygonal shape connecting adjacent lower electrodes.17. The integrated circuit semiconductor device of claim 12, wherein theconcavo-convex structure comprises a first concavo-convex structureformed at a first surface of the support pattern and a secondconcavo-convex structure formed at a second surface of the supportpattern opposite to the first surface of the support pattern, and theconcavo-convex structure has a wave shape or a stair shape.
 18. Anintegrated circuit semiconductor device comprising: a plurality of lowerelectrodes spaced apart from each other on a substrate extending in afirst direction and a second direction perpendicular to the firstdirection; an upper support structure including an upper support patternextending in the first direction and the second direction and having aplurality of first holes through which the plurality of lower electrodespass, and an upper concavo-convex structure having at a surface of theupper support pattern a plurality of upper convex portions extending ina third direction perpendicular to the first direction and the seconddirection, and a plurality of upper concave portions arranged betweenthe plurality of upper convex portions; a lower support structureincluding a lower support pattern extending in the first direction andthe second direction between the substrate and the upper supportstructure, and a lower concavo-convex structure having at a surface ofthe lower support pattern a plurality of lower convex portions extendingin the third direction, and a plurality of lower concave portionsarranged between the lower convex portions; a dielectric film in contactwith the plurality of lower electrodes, the upper support structure, andthe lower support structure; and an upper electrode facing the pluralityof lower electrodes with the dielectric film therebetween.
 19. Theintegrated circuit semiconductor device of claim 18, wherein the upperconcavo-convex structure comprises a first upper concavo-convexstructure formed at a first surface of the upper support pattern and asecond upper concavo-convex structure formed at a second surface of theupper support pattern opposite to the first surface of the upper supportpattern, and the lower concavo-convex structure comprises a first lowerconcavo-convex structure formed at a first surface of the lower supportpattern and a second lower concavo-convex structure formed at a secondsurface of the lower support pattern s opposite to the first surface ofthe lower support pattern.
 20. The integrated circuit semiconductordevice of claim 18, wherein a cross-section of the upper convex portionsand the lower convex portions has a triangular, rectangular, orelliptical shape.